Contribution à l’étude et la réalisation d’un générateur de signaux radiofréquences analogiques pour la radio logicielle intégrale

The increasing density of wireless devices and the associated communication flows sharing the same air interface will require a smart and agile use of frequency resources. This thesis proposes a flexible, low cost and low power disruptive transmitter architecture. It uses a differentiating coding scheme which leverages a mathematical and technological reduction of the energy cost of information conversion. The design of a DAC suited to this architecture is developed and its performances are assessed toward RF signal generation. The measurements of a demonstrator designed in 65 nm CMOS technology bring a proof of concept.Une utilisation intelligente de l’espace Hertzien sera nécessaire pour permettre au nombre croissant d’objets sans-fil connectés de communiquer dans le même espace de propagation. Ces travaux de thèse proposent une architecture d’émetteur radiofréquence flexible, faible coût et faible consommation, en rupture avec les techniques conventionnelles. Cet émetteur est fondé sur un encodage de la dérivée du signal à générer, ce qui permet de réduire le coût énergétique de la conversion de l’information. Un convertisseur numérique analogique compatible avec cette architecture est présenté et ses performances sont évaluées dans le cadre de la génération de signaux radiofréquence. Les résultats de mesures obtenus avec un prototype réalisé en technologie CMOS 65 nm apporte la preuve du concept

Contribution à l'étude et à la réalisation d'un générateur de signaux radiofréquences analogiques pour la radio logicielle intégrale

The increasing density of wireless devices and the associated communication flowssharing the same air interface will require a smart and agile use of frequency resources. Thisthesis proposes a flexible, low cost and low power disruptive transmitter architecture. It usesa differentiating coding scheme which leverages a mathematical and technological reduction ofthe energy cost of information conversion. The design of a DAC suited to this architecture isdeveloped and its performances are assessed toward RF signal generation. The measurementsof a demonstrator designed in 65 nm CMOS technology bring a proof of concept.Une utilisation intelligente de l’espace Hertzien sera nécessaire pour permettre aunombre croissant d’objets sans-fil connectés de communiquer dans le même espace de propagation.Ces travaux de thèse proposent une architecture d’émetteur radiofréquence flexible, faiblecoût et faible consommation, en rupture avec les techniques conventionnelles. Cet émetteur estfondé sur un encodage de la dérivée du signal à générer, ce qui permet de réduire le coût énergétiquede la conversion de l’information. Un convertisseur numérique analogique compatibleavec cette architecture est présenté et ses performances sont évaluées dans le cadre de la générationde signaux radiofréquence. Les résultats de mesures obtenus avec un prototype réalisé entechnologie CMOS 65 nm apporte la preuve du concept

Design of an analog waveform generator dedicated to software radio transmission.

Une utilisation intelligente de l’espace Hertzien sera nécessaire pour permettre aunombre croissant d’objets sans-fil connectés de communiquer dans le même espace de propagation.Ces travaux de thèse proposent une architecture d’émetteur radiofréquence flexible, faiblecoût et faible consommation, en rupture avec les techniques conventionnelles. Cet émetteur estfondé sur un encodage de la dérivée du signal à générer, ce qui permet de réduire le coût énergétiquede la conversion de l’information. Un convertisseur numérique analogique compatibleavec cette architecture est présenté et ses performances sont évaluées dans le cadre de la générationde signaux radiofréquence. Les résultats de mesures obtenus avec un prototype réalisé entechnologie CMOS 65 nm apporte la preuve du concept.The increasing density of wireless devices and the associated communication flowssharing the same air interface will require a smart and agile use of frequency resources. Thisthesis proposes a flexible, low cost and low power disruptive transmitter architecture. It usesa differentiating coding scheme which leverages a mathematical and technological reduction ofthe energy cost of information conversion. The design of a DAC suited to this architecture isdeveloped and its performances are assessed toward RF signal generation. The measurementsof a demonstrator designed in 65 nm CMOS technology bring a proof of concept

Design by Mathematics: Full Software Radio Circuits and Systems in 28nm FDSOI Technology for 5G Standard and Beyond

International audienceThe diversity of communication standards implies the use of multi-band and multi-mode radios. Recent years have seen a wide investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance. It is clearly observed that disruptive solutions are required. The focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. 28nm FDSOI technology from STMicroelectronics will be detailed to demonstrate its strengths in RFIC design. First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide-band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade-off with RF electronics integration in 28nm FDSOI, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide-band capabilities, low power consumption and high order of modulation schemes

Experimental demonstration of a Riemann Pump RF-DAC in 65 nm CMOS

International audienceThis article presents the first experimental results of an integrating Radio-Frequency DAC (RF-DAC) we called the Riemann Pump. This DAC is part of a complete waveform generator architecture based on the quantization of the signal variations and the conversion of the as-obtained digital signal into the analog domain. This technique provides an improvement of the coding efficiency with respect to conventional pulse code modulation conversion schemes. Measurement results confirm the feasibility of this novel topology into silicon CMOS technologies. The conversion efficiency of the prototype realized in 65 nm CMOS is as low as 12 fJ per conversion step

Noise shaping Riemann: an energy efficient data conversion scheme

International audienceThis paper presents a novel conversion scheme for time signals, especially suited for wireless communication applications. The digital/analog data representation paradigm is discussed and critical aspects are determined. It involves digital information coding, two-way digital/analog conversion and their respective efficiency. The proposed conversion scheme relies on a slight oversampling ratio (OSR), combined with a differentiating coding and a 1st order noise shaping loop. It achieves a resolution increased by 2.5 effective number of bits per doubling of the OSR. The resulting conversion efficiency combined with a moderate digital coding complexity leads to a substantial improvement of the energy cost of conversion compared to conventional Nyquist rate architectures. The efficiency gain is even higher for converters limited by thermal noise. It can reach a ten fold improvement for OSR around 10, which makes this architecture a good option for the handling of radio frequency signals

Design by Mathematics of Full Software Radio circuits and systems: methodology and application to 5G standard

International audienceThe diversity of communication standards implies the use of multi-band and multi-mode radios. Recent years have seen a wide investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance. It is clearly observed that disruptive solutions are required. The focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide-band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade-off with RF electronics integration, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide-band capabilities, low power consumption and high order of modulation schemes

Interface de sérialisation 10 Gb/s pour convertisseur numérique/analogique sur-échantillonné à faible consommation

National audienceCet article présente la réalisation en technologie CMOS 65 nm d’une interface parallèle/série haut débit pour un convertisseur numérique/analogique (CNA) sur-échantillonné. Un générateur d’impulsions octophasé permet d’adresser 3 multiplexeurs 8:1 conçus à partir de portes de transfert. La fréquence de fonctionnement est réglable en tension, afin de pouvoir l’asservir sur le processeur bande de base. Les 3 voies numériques haut-débit ainsi générées servent de données d’entrée pour un CNA large bande. L’architecture présentée propose d’employer un CNA intégrateur sur-échantillonné, afin d’améliorer le rapport signal sur bruit ainsi que l’efficacité énergétique de la conversio

Leveraging LoRa Spreading Factor Detection to Enhance Transmission Efficiency

International audienc

Full Software Radio circuits and systems: Design by Mathematics in 28nm FDSOI technology and application to 5G standard

International audienceThe diversity of communication standards implies the use of multi-band and multi-mode radios. Recent years have seen a wide investigation on Software Defined Radio for Cognitive Radio application. But, this is always constrained to multi-standards prospectives while a complete agility of RF transceivers is required. That is why Full Software Radio proposes to challenge a new way of integrating RF circuits and systems by tackling the main issue: transceiving concurrently any RF signal within a very wide band of interest for telecommunication industry, from 0 to 5GHz for instance. It is clearly observed that disruptive solutions are required. The focus of this tutorial will be on the design by mathematics of such RF transceiver design, exploring novel approaches along with a thorough discussion of advanced techniques for these receivers and transmitters towards a revolution in RF integrated circuits and systems. 28nm FDSOI technology from STMicroelectronics will be detailed to demonstrate its strengths in RFIC design.First, a frequency system is presented using a Sampled Analog Signal Processor as a receiver and a Walsh frequency combiner for the transmitter. Then, a temporal system is presented using a wide-band delta analog to digital converter as a receiver and a RF arbitrary waveform generator, named Riemann Pump for the transmitter. The methodology of every approach will be detailed following the same flow: mathematics, trade-off with RF electronics integration in 28nm FDSOI, architecture proposal, high level simulation results, circuit design issues, measurement results. Finally, an application to 5G standard will be addressed by demonstrating the feasibility of such systems to carrier aggregation, wide-band capabilities, low power consumption and high order of modulation schemes